Lattice Nexus 2 Demo – Six Five In the Booth at Lattice Developers Conference 24

Patrick Moorhead: The Six Five is here In the Booth at Lattice Semiconductors Developer Conference. It’s 2024. We are in Silicon Valley, and we have heard product announcements, we’ve heard partners talk, and one of the things that I said in my last interview is that Lattice made FPGAs cool and understandable for people. And one of the things that I appreciate, and I’m a recovering product person and product marketing person, are competitive head-to-head shootouts. And for the second year in a row, we have Deepak here back on the show to take us through some demonstrations. And as we all know in Silicon, for people who love Silicon, power efficiency is very important, especially when it comes to FPGAs. Essentially at a certain application level or certain performance level, what is the power draw? So I’m going to turn it over to Deepak.

Deepak Boppana: Great, thanks Pat. And welcome back to the Lattice Developer Conference. And you’re right, so power is the new currency. And we just announced today Nexus 2, which is our latest platform, small FPGA platform.

Patrick Moorhead: Congrats.

Deepak Boppana: Thank you. And so yeah, we have some exciting demos here based on Certus-N2 which is our first Nexus 2 FPGA. So this one’s all about power efficiency leadership, and basically what we’re showing is a relative power comparison of Certus-N2 FPGA from Lattice, we have the Artix UltraScale+ FPGA from AMD, and the Cyclone 10 GX FPGA from Altera.

Patrick Moorhead: Wait, can we pause just really quickly now? This is this little chip, this is the second generation compared to these somewhat larger looking chips. Are we looking at the right pieces of silicon here?

Deepak Boppana: That’s exactly right. So this is the small one. Good luck finding that. But yes, that’s the Lattice Certus-N2 and yep, compared with other two FPGAs. So yeah, I think as always, many applications in this class of FPGAs. They have the Fmax or the frequency of operation between a hundred to 300 megahertz for a different variety of applications, control plane, data plane. So what you see here is at 300 megahertz Fmax, you can see that Certus-N2 FPGA has up to two times lower power consumption. And as we then modulate and lower the Fmax, let’s say to 150 megahertz, you can see that Certus-N2 FPGA now has up to three times lower power and it keeps getting better at lower frequencies. At a hundred megahertz, it is up to four times. So on average, Certus-N2 FPGA has up to three times lower power consumption than other FPGAs. And that’s really important to simplify thermal management and lower operating costs.

Patrick Moorhead: And just for the audience, just to make it even more real, what types of applications could be running here?

Deepak Boppana: Yeah, that’s a great question. So especially on the edge where these small FPGAs get used even more, with so much computing moving to the edge and edge computing, obviously power and thermal efficiency really matters. So this is across a wide range of applications, in industrial, machine vision, autonomous robots that are battery-based and moving around, consumer, client, compute. So in general, power is something that our customers care about across a variety of applications.

Patrick Moorhead: And this is a grounds-up new design?

Deepak Boppana: Correct. Yes, yes.

Patrick Moorhead: Okay. And it also looks like, just based on the size, that it’s likely using a more modern process as well?

Deepak Boppana: It does. And the good thing is it’s not just about the process, but it’s also the architecture optimization that we always focus on for low power and small size. So we always do a grounds-up kind of optimization, and that’s one of the main reasons there is so much differentiation in power relative to the other FPGAs, which are really water-falling high-density FPGA architecture. So we’ve really architected this for low power, both static power and dynamic power.

Patrick Moorhead: This is great. So we’ll put the details of this in the show notes and let’s move over to the security demo.

Deepak Boppana: Sounds good.

Patrick Moorhead: And we are back with our second demo here, this time with security. And I think everybody can agree security is as important as ever. We can talk about the age of AI, the age of big data. Security has always been important, but it’s even more important now as the risks are higher and potential bad actors have nation-state budgets. Lattice has developed a really good name in security, starting off with data center infrastructure. Like I said in my last video, it’s hard for me to open up one of these servers without seeing a Lattice chip on it. And secondly, made a big name for themselves in telco infrastructure as well, but moving to the edge, which just makes sense in here. So Deepak, what are we looking at here?

Deepak Boppana: Yes, so on this demo we will be showcasing the boot up time and how fast the Certus-N2 FPGA boots up relative to other FPGAs, which as you mentioned is really important in the context of security. So we have the same board here as before with the FPGAs from Lattice, AMD, and Altera and all of the FPGAs are self-configuring from a single external flash device that’s operating at the maximum speed. So yeah, so let’s go ahead and boot up each of the FPGAs and look at the boot up time, starting with the Cyclone 10 GX FPGA from Altera. So we see it takes roughly around 360 milliseconds to boot up. And then the Artix UltraScale+ FPGA is around 260 milliseconds. And then as we do the same and boot up the Certus-N2 FPGA, it’s only 17 milliseconds. It’s like an order of magnitude faster than the other FPGAs, and that’s really, really important in many safety and security applications.

Patrick Moorhead: So these numbers are really low and I’m curious, why do these matter? They seem so low, but why does even being faster matter?

Deepak Boppana: Great question. Every millisecond matters when it comes to security and protection against malicious software and firmware attacks. And to give you an example, Lattice FPGAs are, like you said at the start, widely used in a lot of data center servers. And we are in fact the first chip that powers on and the last chip that powers off. And that, again, goes back to this kind of boot up time capability that we have. And then on top of that is all the security features, including root of trust and PFR or platform firmware resiliency. All of those are solutions that build on top of this capability.

Patrick Moorhead: No, I appreciate this. And I remember a day when people were booting off the host CPU and pretty much the standard this day in the data center and in telco is the first thing that lights up is an FPGA.

Deepak Boppana: Absolutely right. And as you also touched on, the security is something that’s proliferating so fast across different industries and communications infrastructure, wireless base stations, radio heads, we see a similar trend as well. And then moving to the edge, across industrial, automotive. So this is something that is going to be… It has always been and will continue to be one of the cornerstones of our FPGAs.

Patrick Moorhead: Great. Let’s head over and meet up with Dan and we’re going to be talking more security in our final demonstration.

Daniel Newman: All right, well, those first two demos were great. We’ve headed over to the other side here. This event is big, it takes up quite a bit of space. Deepak, let’s tie this all together here. We talked a little bit about performance, we’ve talked a little bit about security, but let’s tie everything together here in this third demo.

Deepak Boppana: Absolutely. Yeah. In fact, this demo does exactly that. It showcases how the unique combination of low power and fast boot up performance together can be used to even further reduce the power consumption, which is again, really important for edge applications. So you have the same board here as before, the same FPGAs from Lattice, AMD, and Altera. And all of these are connected over these coax cables to that oscilloscope. And basically what the oscilloscope is showing is the monitoring rate, which is the number of times the FPGAs turn on and off per second. And that goes back to the boot up time. And we showed in the earlier demo the significant difference in boot up time.

Just to give you an example of an application, like even AI, Edge AI, which is a pretty common use case for FPGAs, monitoring the sensor data to detect humans or objects is something that’s part of that kind of use case. And the thing is you don’t need to be on all the time to detect the sensor data. So that’s basically a good application where in some cases like AI PCs, you don’t need to be so fast in terms of detecting the output. In some AI use cases like autonomous robots, you have to have a faster monitoring rate because they’re more safety critical applications. So that’s what we show in this demo is how does the power consumption change as we increase or decrease the monitoring rate of the FPGAs.

Daniel Newman: So you gain performance, you improve the boot cycle time, and of course, that also does have security implications, which you talked about in the second demo, which is really good. And from what I’m seeing here, Nexus is showing leadership in terms of both these categories.

Deepak Boppana: Absolutely right. And then this actually shows together how that multiplies even further. So you can see that at a monitoring rate of 10 times per second… Again, that means the FPGAs are turning on and off 10 times. You can see the power difference is up to 6x lower power for the Certus-N2 FPGAs. And as we continue to change the monitoring rate to eight times per second and six times per second, four times per second, you can see that difference in power consumption further amplifies and Certus-N2 on average has up to 10 times lower power consumption than the other FPGAs.

Daniel Newman: And given how much attention right now is being paid to power consumption in these new AI data centers, of course, is an area, for instance, or with new more power-consuming AI PCs in these areas, a lot of attention. So this makes a difference. And of course, while we’re showing something for one FPGA, many data centers, these can be hundreds, thousands, hundreds of thousands and more. I think, what, you ship a quarter of a billion of these things?

Deepak Boppana: That’s right, yeah.

Daniel Newman: In a year. So what I’m saying is you’re sort of thinking about how to reduce power, it really does add up, it’s really meaningful. And this can be a solution as people are trying to take this into consideration.

Deepak Boppana: Absolutely right. Especially again, as more and more intelligence moves to the edge, there’s a lot more computing needed. And this really helps in those types of use cases, including again, Edge AI. And again, it’s all about milliseconds and milliwatts. I think that’s the level at which the Lattice FPGAs operate, and that’s again, really important for AI and security applications.

Daniel Newman: Well, Deepak, thanks so much for showing us this. Thanks for taking Patrick and myself through all of these demos. It’s been great being here with you at the Lattice Developer Conference, Lattice Semiconductor Developer Conference 2024. Look forward to seeing you again next year. Always enjoy doing these demos with you.

Deepak Boppana: Yep, my pleasure. Thank you. And also, please check out… We have the whole ecosystem of more than 80 plus partner demos in the technology showcase as well.

Daniel Newman: And that is a message for all of you to check all of this out. Check the links out in the show notes. We appreciate you being part of the community. Hit that subscribe button, be part of the event from Patrick and I. Join us for all the conversations we had here. And of course, be part of all of the great coverage here on The Six Five. But for this one, I’ve got to say goodbye to everybody. Thanks for tuning in. We’ll see you all later.